Method and device for converting a quantized digital value

ABSTRACT

The invention concerns a method and a device for converting an input digital value quantized in accordance with a first quantization factor and encoded on at most n1 bits, into an output digital value quantized in accordance with a second quantization factor and encoded on at most n2 bits. The method comprises the steps of: multiplying the input digital value by an integer B, encoded on at most β bits, so as to generate an intermediate digital value; and dividing, in fixed point, the first intermediate digital value by the number 2 α , where α is an integer not greater than n1+β, generating the output digital value. The number B/2 α  is substantially equal to the ratio of the second quantization factor over the first quantization factor. Additionally, the divider means comprise a Sigma-Delta modulator.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to the field of fixed-point digital signalprocessing. Applications may be found for it in any fixed-point digitalsystem, and particularly in the digitally modulated synthesizers used inthe radio transmitters and the radio transceivers of a digitalradiocommunication system.

2. Related Art

For carrying out operations on binary numbers, a floating-point digitalsystem comprises software resources such as a correctly programmed DSP(Digital Signal Processor). A fixed-point system, however, onlycomprises sequential logic circuits such as digital adders, digitalmultipliers, shift registers or the like.

The binary numbers which are processed by a fixed-point digital systemencode quantized values corresponding to a real value X (for example thevariable value of the radio signal received by a radio receiver, or theconstant value of the frequency of a radio channel). These quantizednumbers are represented by integers between zero and 2^(n)−1—where n isthe number of bits used for encoding the information—if the value X isalways positive, or between −(2^(n)−1) and 2^(n)−1 if the value X issigned (that is, if it can be negative). By convention, Xq denotes thequantized value which is obtained from the real value X by a quantizingoperation. For linear quantizing, the correspondence between the realvalue X (so-called real information) and the quantized value Xq(so-called quantized information) is given by the relation:Xq=round(X×Cq)   (1)

where Cq is a real number referred to as the quantization coefficient.

The quantization of the system is determined by the number Cq inrelation with the number n. The quantization coefficient Cq is suchthat:

$\begin{matrix}\left\{ \begin{matrix}{{{{round}\;\left( \left| {X(t)} \middle| {\times {Cq}} \right. \right)} \leq {2^{n - 1} - 1}},{\forall t},{{if}\mspace{14mu}{the}\mspace{14mu}{information}\mspace{14mu} X\mspace{14mu}{is}\mspace{14mu}{signed}}} \\{{{{round}\;\left( {{X(t)} \times {Cq}} \right)} \leq {2^{n} - 1}},{\forall t},{otherwise}}\end{matrix} \right. & (2)\end{matrix}$where |x| denotes the absolute value operator of the real variable x.

The act of quantizing the information X creates an error, referred to asthe quantization error and denoted by e, such that:

$\begin{matrix}{e = {{X - \frac{Xq}{Cq}} = {X - \frac{{round}\left( {X \times {Cq}} \right)}{Cq}}}} & (3)\end{matrix}$

The error e is of course variable, inasmuch as it depends on the valueX. According to the properties of the rounding function, the error e isalways such that

${e} \leq {\frac{1}{2 \times {Cq}}.}$The maximum value of the quantization error, denoted by e_(max), istherefore given by:

$\begin{matrix}{e_{\max} = \frac{1}{2 \times {Cq}}} & (4)\end{matrix}$

The inverse of the quantization coefficient Cq is the resolution of thedigital system, that is to say the smallest variation of the realinformation which is distinguishable in the quantized information. Putanother way,

$\frac{1}{Cq}$is such that if

$X = {\frac{1}{Cq} + X^{\prime}}$then Xq=1+Xq′.

Optimization of the dynamic range of the system generally leads to thequantization being defined by choosing Cq such that:

$\begin{matrix}\left\{ \begin{matrix}{{{Cq} = \frac{\max\left( \left| {X(t)} \right| \right)}{2^{n - 1} - 1}},{\forall t},{{if}\mspace{14mu}{the}\mspace{14mu}{information}\mspace{14mu} X\mspace{14mu}{is}\mspace{14mu}{signed}}} \\{{{Cq} = \frac{\max\left( {X(t)} \right)}{2^{n} - 1}},{\forall t},{otherwise}}\end{matrix} \right. & (5)\end{matrix}$

Certain systems dictate the quantization of the digital data, forexample in order to be compatible with analog signals afterdigital-analog conversion of a quantized signal. In this case, there isa quantization error majored in modulus by

${e_{\max} = \frac{1}{2 \times {Cq}}},$where Cq is the corresponding quantization coefficient. However, it mayarise that this resolution is insufficient for representing some or allof the digital signals of the system.

On the other hand, certain digital systems use constant digital values.In a radio transmitter or receiver, for example, such a digital constantmay represent the central frequency of a radio channel. In this case,the situation may be encountered in which a quantization error affectingthe digital constant (this error being systematic inasmuch as it doesnot vary) exceeds the maximum tolerable error for digital representationof this constant. If the system does not dictate the quantization of thedigital data, then the systematic quantization error affecting aspecific digital constant K may be reduced, albeit this may mean thatthe dynamic range of the system is not optimized, by choosing thequantization coefficient Cq such that

${{K - \frac{{round}\left( {K \times {Cq}} \right)}{Cq}} \leq e_{d} \leq e_{\max}},$where e_(d) is the maximum tolerable error for digital representation ofthe constant K. This is not always possible in a system which dictatesthe quantization of the digital data, such as a digitally modulatedfrequency synthesizer, for example.

BRIEF DESCRIPTION OF THE INVENTION

This is why a first aspect of the present invention reduces thequantization errors of a digital signal and or to digitally correct asystematic quantization error of a digital value (in particular aconstant value) without any constraint governing the quantization, thatis to say without any constraint governing n and Cq.

It is moreover possible for digital data obtained from two subsystems,having respective quantizations determined by distinct quantizationcoefficients, to be used in a digital system only if one of the twoquantization coefficients is an integer multiple of the other.

Specifically, if data obtained from a first subsystem, having aquantization determined by a first coefficient Cq1, are intended to beused in the same digital system with digital data obtained from a secondsubsystem, having a quantization determined by a second coefficient Cq2different to Cq1, then Cq1 and/or Cq2 must be chosen such that Cq2=r×Cq1or Cq1=r×Cq2, where r is an integer.

The data can then be rendered uniform by multiplying the data of thefirst subsystem or of the second subsystem, as applicable, by r. This,however, is only possible if at least one of the subsystems does notdictate the quantization of the digital data.

This is why the first aspect of the present invention allows a pluralityof digital systems to be connected together, while insuringcompatibility of the data but without any constraints governing theirrespective quantizations.

Said first aspect of the invention thus provides a method for convertinga digital input value quantized according to a first quantizationcoefficient and encoded over and most n1 bits, into a digital outputvalue quantized according to a second quantization coefficient andencoded over at most n2 bits, where n1 and n2 are nonzero integers.

The method comprises the steps consisting in:

a) multiplying the digital input value by an integer B encoded over atmost β bits, where β is a nonzero integer, in order to generate a firstintermediate digital value encoded over at most n1+β bits; and

b) fixed-point dividing said first intermediate digital value by thenumber 2^(α), where α is an integer less than or equal to n1+β, in orderto generate said digital output value.

According the invention, the number

$\frac{B}{2^{\alpha}}$is substantially equal to the ratio of said second quantizationcoefficient to said first quantization coefficient. Step b) isfurthermore carried out by means of a sigma-delta modulator (Σ-Δmodulator). This is preferably a 1^(st) order Σ-Δ modulator, which isthe simplest to use.

It will be noted that digital/digital conversion is involved, that is tosay both the digital output value and the digital input value arequantized digital values. What changes is the quantization of thisdigital value. In particular, the Σ-Δ modulator is a digital/digitalmodulator.

A second aspect of the invention also provides a device for converting adigital input value quantized according to a first quantizationcoefficient and encoded over at most n1 bits, into a digital outputvalue quantized according to a second quantization coefficient andencoded over at most n2 bits, where n1 and n2 are nonzero integers.

The device comprises multiplier means for multiplying the digital inputvalue by an integer B encoded over at most β bits, where β is a nonzerointeger. These multiplier means generate a first intermediate digitalvalue encoded over at most n1+β bits. The device furthermore comprisesdivider means for fixed-point dividing said first intermediate digitalvalue by the number 2α, where a is an integer less than or equal ton1+β. These divider means generate said digital output value.

According the invention, the number

$\frac{B}{2^{\alpha}}$is substantially equal to the ratio of said second quantizationcoefficient to said first quantization coefficient. Said divider meansfurthermore comprise a sigma-delta (Σ-Δ) modulator.

As is known, a Σ-Δ modulator is a circuit synchronous with the samplingfrequency of the input signal. It performs quantization “noise shaping”at the high frequencies. A signal with a reduced quantization noise atthe useful frequencies is recovered at the output of the Σ-Δ modulator.On average, that is to say at a low frequency compared with the samplingfrequency, the gain of the device is equal to

$\frac{B}{2^{\alpha}}.$

A digital output value which corresponds, with good precision, to thedigital input value multiplied by the ratio of said second quantizationcoefficient to the first quantization coefficient is therefore obtainedat the output of the Σ-Δ modulator.

The principle of the invention is based on the following concept. Inwhat follows, Sq1 will denote the digital input value (quantizedinformation) and Cq1 will denote the first quantization coefficient.Likewise, Sq2 will denote the digital output value (quantizedinformation) and Cq2 will denote the second quantization coefficient.Lastly, S will denote the real value (unquantized information)corresponding to Sq1 and Sq2. The relations below are then written:

$\begin{matrix}{{Sq2} = {{round}\;\left( {S \cdot {Cq2}} \right)}} & (6) \\{{{whence}\mspace{14mu}{Sq2}} \cong {{round}\;{\left( {S \cdot {Cq1}} \right) \cdot \frac{Cq2}{Cq1}}}} & (7) \\{{{whence}\mspace{14mu}{Sq2}} \cong {{Sq1} \cdot \frac{Cq2}{Cq1}}} & (8) \\{{{that}\mspace{14mu}{is}\mspace{14mu}{to}\mspace{14mu}{say}\mspace{14mu}{Sq2}} \cong {{Sq1} \cdot \frac{B}{2^{\alpha}}}} & (9) \\{{{with}\mspace{14mu}\frac{Cq2}{Cq1}} \cong \frac{B}{2^{\alpha}}} & (10)\end{matrix}$

It can be seen that the effect of the invention is to implement relation(9) by using relation (10). It therefore makes it possible to convertthe digital value Sq1 into a digital value Sq2, which are informationquantized according to different respective quantization coefficientsCq1 and Cq2 and which both correspond to the same real information S,without any restrictive assumption being made about the relation betweenone of these quantization coefficients and the other.

The invention thus makes it possible to reduce the quantization erroraffecting a variable or constant real value. Specifically, it issufficient to choose the first quantization coefficient Cq1 so as tominimize the quantization error affecting the digital value Sq1, and toconvert this value by delivering it as a digital input value to a deviceaccording to the invention, in order to obtain a digital output valueSq2 quantized according to a second quantization coefficient Cq2, whichwill be chosen as being that of the quantization of the subsystemneeding to use the digital input value. The quantization error affectingthe digital value Sq2 can thus be reduced without any constraintsgoverning the quantization of the subsystem.

This is shown by the following calculation of the quantization error eaffecting the real value S, in the case when the device according to theinvention is used.

The expression for e is given by:

$\begin{matrix}{e = {S - \frac{\left( {{Sq1} \cdot \frac{B}{2^{\alpha}}} \right)}{Cq2}}} & (11)\end{matrix}$

But Sq1=round(S.Cq1).

Whence

${{{Sq}\; 1}} \leq {{{{S.{Cq}}\; 1}} + {\frac{1}{2}\mspace{14mu}{and}}\mspace{14mu} - {{Sq}\; 1}} \leq {{{- {S.{Cq}}}\; 1} + \frac{1}{2}}$

From this it follows:

$e \leq {S - \frac{\left( {S \cdot {Cq1} \cdot \frac{B}{2^{\alpha}}} \right)}{Cq2} + {\frac{1}{2} \cdot \frac{\left( \frac{B}{2^{\alpha}} \right)}{Cq2}}}$${{i.e.\mspace{14mu}{e}} \leq {{{S} \cdot {{1 - {\frac{Cq1}{Cq2} \cdot \frac{B}{2^{\alpha}}}}}} + {\frac{1}{2} \cdot \frac{\left( \frac{B}{2^{\alpha}} \right)}{Cq2}}}} = {{{S} \cdot {{1 - {\frac{Cq1}{Cq2} \cdot \frac{B}{2^{\alpha}}}}}} + {\frac{1}{2 \cdot {Cq1}} \cdot \left( {\frac{Cq1}{Cq2} \cdot \frac{B}{2^{\alpha}}} \right)}}$

The choice of B and α gives

${{\frac{Cq1}{Cq2} \cdot \frac{B}{2^{\alpha}}} = {1 + ɛ}},$where ε denotes a negligible quantity compared with unity (ε=o(1)). Itthen follows:

$\begin{matrix}{{e} \leq {{{S} \cdot {ɛ}} + {\frac{1}{2 \cdot {Cq1}} \cdot \left( {1 + ɛ} \right)}} \cong {{{S} \cdot {ɛ}} + \frac{1}{2 \cdot {Cq1}}}} & (12)\end{matrix}$

The quantization error of the quantized value Sq2 obtained by the methodaccording to the invention is therefore at most equal to the sum, on theone hand, of the maximum quantization error of the value Sq1 quantizedaccording to the quantization coefficient Cq1 and, on the other hand, animage of the real value S which will in general be negligible. With aquantization according to the quantization coefficient Cq2, there wouldhave been an error majored by

$\frac{1}{2 \cdot {Cq2}}.$

In order to reduce the quantization error affecting the value of Sq2 inthe subsystem that uses this value, the value of Cq1 will advantageouslybe chosen such that Cq1 is greater than Cq2 (Cq1>Cq2).

In the particular case when the digital value in question is an integer,the first digital input value Sq1 is equal to the real value S (Sq1=S)and the first quantization coefficient Cq1 is equal to unity (Cq1=1).The quantization error affecting Sq1 is then zero, and the quantizationerror affecting Sq2 is then minimal. In this case, relation (12) iswritten:e=S×ε  (13)

The invention furthermore makes it possible for a digital value Sq1 of afirst subsystem, having a first specific quantization, to be adapted toa second specific quantization which is associated with a secondsubsystem that needs to use this digital value, without any constraintsgoverning the respective quantizations of these two subsystems.Specifically, it is sufficient to deliver this digital value Sq1 as adigital input value to a device according to the invention, in whichsaid first quantization coefficient Cq1 is chosen to be equal to that ofsaid first specific quantization, and in which said second quantizationcoefficient Cq2 is chosen to be equal to that of said second specificquantization.

A third aspect of the invention provides a digitally modulated frequencysynthesizer, comprising a phase-locked loop comprising a variable-ratiofrequency divider in the return path. The division ratio of said divideris controlled by a digital value obtained in particular from a realvalue corresponding to the central frequency of a radio channel. Thesynthesizer furthermore comprises a conversion device as defined, forreducing the quantization error affecting said real value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a device according to the invention;

FIG. 2 is a flow chart of the steps in a method according to theinvention;

FIG. 3 is a block diagram of a first embodiment of the device in FIG. 1;

FIG. 4 is a block diagram of a second embodiment of the device in FIG.1;

FIG. 5 is a diagram illustrating the application of a mask to a specificdigital value;

FIG. 6 is a block diagram of a third embodiment of the device in FIG. 1;and

FIG. 7 is a block diagram of a digitally modulated synthesizerincorporating a device according to the invention.

DESCRIPTION OF THE PREFERED EMBODIMENTS

FIG. 1 represents the block diagram of a device according to theinvention.

The device comprises an input 1 for receiving a digital input value Sq1,which is a quantized value of a variable or constant real value. Thevalue Sq1 is quantized according to a first quantization coefficient Cq1and encoded over at most n1 bits, where n1 is a nonzero integer. Thedevice also comprises an output 2 for delivering a digital output valueSq2. The value Sq2 is quantized according to a second quantizationcoefficient Cq2 and encoded over at most n2 bits, where n2 is a nonzerointeger.

The device also comprises means, such as a digital multiplier 10, formultiplying the digital input value Sq1 by an integer B encoded over atmost β bits, where β is a nonzero integer. The means 10 generate a firstintermediate digital value C encoded over at most n1+β bits.

The device further comprises divider means for fixed-point dividing saidfirst intermediate digital value C by the number 2^(α), where α is aninteger less than or equal to n1+β. These divider means generate thedigital output value Sq2.

According to the invention, these divider means comprise a sigma-deltamodulator 20, which receives the intermediate value C as input anddelivers the digital output value Sq2 as output. The Σ-Δ modulator is adigital/digital modulator, which receives as input a digital valueencoded over n1+β bits and delivers as output a digital value encodedover n1+β+1−α bits. It is preferably a 1^(st) order Σ-Δ, modulator,which is the simplest to use. Embodiments with a higher-order Σ-Δmodulator may nevertheless be envisaged.

According to the invention, the number

$\frac{B}{2^{\alpha}}$is furthermore substantially equal to the ratio

$\frac{Cq2}{Cq1}$of the second quantization coefficient Cq2 to the first quantizationcoefficient Cq1.

As mentioned in the introduction, such a device converts the digitalvalue Sq1, quantized according to the quantization coefficient Cq1, intothe digital value Sq2, quantized according to the quantizationcoefficient Cq2.

FIG. 2 is a flow chart illustrating the steps in a method according tothe invention. The method is carried out by a device as described abovewith reference to FIG. 1.

In a step 100, the digital input value Sq1 is received.

In a step 200, the value Sq1 is multiplied by the number B in order togenerate the first intermediate digital value C.

In a step 300, the first intermediate digital value C is fixed-pointdivided by the number 2^(α) in order to generate the digital outputvalue Sq2. According to the invention, step 300 is carried out by meansof a sigma-delta modulator. The number

$\frac{B}{2^{\alpha}}$is furthermore substantially equal to the ratio

$\frac{Cq2}{Cq1}.$

The diagram in FIG. 3 illustrates a first embodiment of a deviceaccording to the invention, which is suitable for carrying out a firstvariant of the method.

In this first embodiment, the sigma-delta modulator 20 comprises means21 such as a digital adder, which receive as input the firstintermediate digital value C as a first operand, on the one hand, and adigital error value E as a second operand, on the other hand. The latteris encoded over at most α bits. The means 21 deliver as output a secondintermediate digital value D encoded over at most n1+β+1 bits.

The device further comprises selection means 23, such as a digitaldiscriminator, for selecting the n2 most significant bits of the secondintermediate digital value D as the digital output value Sq2, and forselecting the α least significant bits of said second intermediatedigital value D as the digital error value E. It follows that n2 isequal to n1+β+1−α. The means 23 receive the value D as input and deliverthe value Sq2 as well as the value E as output.

A digital discriminator is a circuit which separates the khigh-significance bits and the j low-significance bits of a givendigital input value in order to generate two digital output values,encoded respectively over k bits and over j bits and each having as itsvalue the value corresponding respectively to said k high-significancebits and to the j low-significance bits. Here, the discriminator 23separates the n1+β+1−α most significant bits of the second intermediatedigital value D, on the one hand, and the α least significant bits ofthe value D, on the other hand.

The diagram in FIG. 4 illustrates a second embodiment of a deviceaccording to the invention, which is suitable for carrying out a secondvariant of the method.

In this second embodiment, the selection means 23 of the device comprisean operator 24 for shifting to the right by α bits. Such an operator isformed, for example, with the aid of a properly controlled shiftregister. This operator 24 receives as input the n1+β+1 bits of thesecond intermediate digital value D. It delivers as output the n1+β+1−αmost significant bits of the second intermediate digital value D as adigital output value Sq2.

The selection means 23 furthermore comprise means 25 for applying a maskto the second intermediate digital value D.

Such a mask is represented in FIG. 5 with the reference M. It is adigital value stored in an appropriate register and having at mostn1+β+1 bits, the n1+β+1−α most significant bits of which are equal tothe logical value 0 and the α least significant bits of which are equalto the logical value 1. When it is combined with the second intermediatedigital value D in an operation of the logical AND type, it makes itpossible to select the α least significant bits of said secondintermediate digital value D.

Stated otherwise, the means 25 receive as input the n1+β+1 bits of thesecond intermediate digital value D. They deliver as output the n1+β+1−αmost significant bits of the second intermediate digital value D as thedigital error value E.

The diagram in FIG. 6 illustrates a third embodiment of a deviceaccording to the invention, which is suitable for carrying out a thirdvariant of the method.

In this third embodiment, the selection means 23 of the device stillcomprise an operator 24 for shifting to the right by α bits, which hasthe same function as the operator 24 of the device in FIG. 4.

The selection means 23 further comprise an operator 26 for shifting tothe left by α bits, which receives as input the n1+β+1−α bits of thedigital output value Sq2 and delivers as output a third intermediatedigital value F, encoded over at most n1+β+1 bits. The operator 26 is,for example, a properly controlled shift register. They furthermorecomprise an operator 27 for taking the difference between theintermediate digital values F and C. The operator 27 is, for example, adigital subtracter. It receives the third intermediate digital value Fas a first operand, and the first intermediate digital value C as asecond operand. It delivers as output the digital error value E.

In each of the three embodiments described above with reference to FIGS.3, 4 and 6, the device preferably comprises an operator 22 that appliesa unitary delay to the digital error value E for synchronizationreasons. Stated otherwise, the error signal E is delivered to the inputof the adder means 21 through a unitary delay operator 22.

FIG. 6 shows the diagram of a digitally modulated frequency synthesizer,more commonly referred to by the term DMS, which incorporates a deviceaccording to the invention.

Such a circuit can be used for generating a frequency- orphase-modulated radiofrequency signal (in the UHF band lying between 400and 600 MHz). Applications may be found for it in the radio transmittersor transceivers of a radiocommunication system, particularly in the basestations and/or the mobile terminals of such a system.

A DMS has a structure which is derived from the structure of afractional N frequency synthesizer, and makes it possible to generate afrequency- or phase-modulated periodic signal.

The DMS includes a phase-locked loop or “PLL”, comprising aphrase/frequency comparator 11 or “PFC”, a loop filter 12 such as anintegrator, and a voltage controlled oscillator 13 or “VCO” in series ina forward channel, and as well as a frequency divider 14 in a returnchannel. The VCO delivers as output a signal S_(out) which is the outputsignal of the DMS, the instantaneous frequency of which is f_(out). ThePFC receives at a first input a reference signal S_(ref) having areference frequency f_(ref), and at a second input a signal S_(div)delivered by the frequency divider 14 on the basis of the signalS_(out).

For conventional fractional N synthesis, the frequency divider 14 is avariable-ratio divider making it possible to produce the signal S_(div)by dividing the frequency f_(out) of the signal S_(out) by a divisionratio, which alternately has the value of an integer N for a part of thetime T1 and the integer N+1 for the rest of the time T2. In this way,the frequency f_(out) of the output signal S_(out) is given as afunction of the frequency f_(ref) of the reference signal S_(ref) by:

$\begin{matrix}{f_{out} = {\left( {N + \frac{T1}{{T1} + {T2}}} \right) \times f_{ref}}} & (14)\end{matrix}$

In a digitally modulated synthesizer, the frequency divider 14 includesan input for controlling the division ratio. This ratio is fixed by thevalue stored in a specific accumulator. In order to prevent spuriouslines, due to periodicity of the division ratio changes from N to N+1and back again, from occurring in the spectrum of the output signalS_(out), however, a DMS known in the prior art furthermore includes amodulator 15 of the digital/digital Σ-Δ modulator type.

The modulator 15 includes an input which receives a digital frequency-or phase-modulation value S_(mod) encoded over k bits, and an outputwhich delivers a digital value S′_(mod), corresponding to the processedvalue S_(mod) and encoded over j bits. The output of the modulator 15 isconnected to a first input of a digital adder 16, the second input ofwhich receives a digital value N_(o) that defines the bottom of thefrequency band addressed by the synthesizer. The output of the adder 16delivers a digital value S_(c). It is connected to the control input ofthe divider 14 in order to deliver the value S_(c) to it.

The DMS also comprises a second digital adder 17, a first input of whichreceives a digital value S_(info) and a second input of which receives adigital value S_(ch2). The output of the adder 17 delivers theaforementioned digital frequency- or phase-modulation value S_(mod). Thedigital value S_(info) contains the modulation information (modulatingsignal), that is to say the useful information to be transmitted. Thedigital value S_(ch2) corresponds to the central frequency of the radiochannel (after the aforementioned value N_(o) has been added).

The digital values S_(info), S_(ch2), S_(mod) and S′_(mod) and N_(o) arevalues that are quantized according to a quantization coefficient Cq2 ofthe digital system constituted by the DMS.

According to the invention, the value S_(ch2) is delivered by aconverter device 18 as described above with reference to FIGS. 2 to 6,on the basis of a digital value S_(chq1) stored in an appropriateregister. The quantized values S_(ch1) and S_(ch2) correspond to a realvalue, namely the central frequency of the channel, denoted below byF_(ch). The real value F_(ch) is constant, because the central frequencyof the channel is constant. If the device 18 was not there, the realvalue F_(ch) would be directly quantized according to the quantizationcoefficient Cq2 of the digital system constituted by the DMS. However,the DMS presented here incorporates a device 18 according to theinvention in order to reduce the quantization error affecting thequantized digital value corresponding to the real value F_(ch) (which isa systematic error since this value is constant). Stated otherwise, theDMS comprises a device 18 for converting the digital value S_(ch1) intoa digital value S_(ch2), which is quantized according to thequantization coefficient Cq2 of the digital system constituted by theDMS.

To apply that which has been described above, a choice is therefore madeto implement a converter device 18 of the type described above, forwhich Cq1 is equal to unity (Cq1=1, because the real value F_(ch) isinteger) and for which Cq2 is the quantization coefficient of thequantization of the DMS.

A numerical example for illustrating the advantages offered by theinvention in this application will be given below. In this example:

-   -   F_(ref)=9.6 MHz (megahertz);    -   k=22;    -   j=4;    -   F_(ch)=400017.5 kHz (kilohertz);    -   N_(o)=round(395 MHz/F_(ref));    -   e_(d)=4 Hz (hertz).

The frequency resolution of such a DMS is given by

$\frac{F_{ref}}{2^{k - j}},$where k is the number of bits at the input of the sigma-delta modulator15, and where j is the number of bits at the output of this modulator.The frequency resolution of the DMS, that is to say

$\frac{1}{Cq2},$is therefore:

$\frac{1}{Cq2} = {\frac{F_{ref}}{2^{k - j}} = {\frac{9.6 \cdot 10^{6}}{2^{18}} \approx {36.62\mspace{14mu}{Hz}}}}$

The value F_(min), corresponding to the bottom of the frequency bandaddressed by the DMS, is determined by the digital value N_(o) accordingto the relation F_(min)=N_(o)×F_(ref). Here, therefore,F_(min)=41×9.6·10⁶=393.6 MHz.

Let us first consider what the situation would be without the device 18according to the invention, that is to say if Sch1=Sch2. We would have:Fch2=round[(F _(ch) −F _(min)).Cq2]=175241

The systematic quantization error affecting the central frequency of theradio channel would therefore be:

$e = {F_{ch} - \left( {\frac{Fch2}{Cq2} + F_{\min}} \right)}$

i.e.:

$e = {{{400017.5 \cdot 10^{3}} - \left( {\frac{175241}{Cq2} + {393.6 \cdot 10^{6}}} \right)} = {{- 17.08}\mspace{14mu}{Hz}}}$

This value exceeds (in absolute value) the acceptable error e_(d).

Let us now consider what happens with the conversion device 18 accordingto the invention. Since the signal intended to be represented isinteger, we have Cq1=1.

The following approximation is chosen:

${{Cq2} \approx \frac{B}{2^{\alpha}}} = {\frac{229065}{2^{23}}.}$In other words, a choice is made to implement a device according to theinvention with B=229065 and α=23.

The quantization error can be determined by using the relation (13)given in the introduction, which is valid in the case when the realdigital value at the input of the device (here, the constant valueF_(ch)−F_(min)) is an integer. It will be recalled that this relation isthen written:

$e = {{S \cdot ɛ} = {{{S \cdot \frac{Cq1}{Cq2}}\;\frac{B}{2^{\alpha}}1} \cong {2.17\mspace{14mu}{Hz}}}}$

where S denotes the real digital value at the input of the device (hereF_(ch)).

Whence it follows that e≅2.17 Hz. The goal of a quantization error lessthan 4 Hz affecting the value of the central frequency of the radiochannel has therefore indeed been achieved, without having to modify thequantization of the system. Here, the invention makes it possible toreduce the systematic quantization error affecting the value of thecentral frequency of the radio channel from 17 Hz to 2 Hz.

A better result could be obtained by increasing the precision of theapproximation for

$\frac{Cq2}{Cq1},$but at the cost of increasing the number β and the number α.

1. A method for converting a digital input value quantized according toa first quantization coefficient and encoded over at most n1 bits, intoa digital output value quantized according to a second quantizationcoefficient and encoded over at most n2 bits, where n1 and n2 arenonzero integers, comprising the steps of: multiplying the digital inputvalue by an integer B encoded over at most β bits, where β is a nonzerointeger, so as to generate a first intermediate digital value encodedover at most n1+β bits; and fixed-point dividing said first intermediatedigital value by a number 2^(α), where α is an integer less than orequal to n1+β, so as to generate said digital output value, wherein anumber $\frac{B}{2^{\alpha}}$ is substantially equal to the ratio ofsaid second quantization coefficient to said first quantizationcoefficient; and wherein the step of fixed point dividing is carried outby means of a sigma-delta modulator.
 2. The method as claimed in claim1, wherein the step of fixed-point dividing comprises the steps of:adding said first intermediate digital value, on the one hand, and adigital error value encoded over at most α bits, on the other hand, soas to generate a second intermediate digital value encoded over at mostn1+β+1 bits; selecting a given number n2 of the most significant bits ofsaid second intermediate digital value as the digital output value,where n2 is equal to n1+β+1−α; and selecting a given number α of theleast significant bits of said second intermediate digital value as thedigital error value.
 3. The method as claimed in claim 2, wherein thesteps of selecting are carried out together with the aid of adiscriminator for separating the n1+β+1−α most significant bits of thesecond intermediate digital value, on the one hand, and the α leastsignificant bits of said second intermediate digital value, on the otherhand.
 4. The method as claimed in claim 2, wherein the step of selectingthe n2 most significant bits is carried out via an operation of shiftingto the right by α bits, which is applied to the n1+β+1 bits of thesecond intermediate digital value.
 5. The method as claimed in claim 4,wherein the step of selecting the α least significant bits is carriedout by applying to the second intermediate digital value a mask havingat most n1+β+1 bits, the n1+α+1−α most significant bits of which areequal to the logical value 0 and the α least significant bits of whichare equal to the logical value
 1. 6. The method as claimed in claim 4,wherein the step of selecting the α least significant bits is carriedout, on the one hand, by an operation of shifting to the left by α,which is applied to the n1+β+1−α bits of the digital output value forgenerating a third intermediate digital value encoded over at mostn1+β+1 bits and, on the other hand, by a difference operation betweensaid third intermediate digital value and said first intermediatedigital value.
 7. The method as claimed in claim 1, wherein neither thefirst quantization coefficient nor the second quantization coefficientis an integer multiple of the other.
 8. A device for converting adigital input value quantized according to a first quantizationcoefficient and encoded over at most n1 bits, into a digital outputvalue quantized according to a second quantization coefficient andencoded over at most n2 bits, where n1 and n2 are nonzero integers,comprising: multiplier means for multiplying the digital input value byan integer B encoded over at most β bits, where β is a nonzero integer,so as to generate a first intermediate digital value encoded over atmost n1+β bits; and divider means for fixed-point dividing said firstintermediate digital value by the number 2α, where α is an integer lessthan or equal to n1+β, so as to generate said digital output value,wherein a number $\frac{B}{2^{\alpha}}$ is substantially equal to theratio of said second quantization coefficient to said first quantizationcoefficient; and wherein said divider means comprise a sigma-deltamodulator.
 9. The device as claimed in claim 8, wherein the sigma-deltamodulator is a 1^(st) order sigma-delta modulator.
 10. The device asclaimed in claim 9, wherein the sigma-delta modulator comprises: addermeans which receive as input said first intermediate digital value as afirst operand, on the one hand, and a digital error value encoded overat most α bits as a second operand, on the other hand, and which deliveras output a second intermediate digital value encoded over at mostn1+β+1 bits; selection means for selecting a given number n2 of the mostsignificant bits of said second intermediate digital value as thedigital output value, where n2 is equal to n1+β+1−α; and for selectingthe a given number α of the least significant bits of said secondintermediate digital value as the digital error value.
 11. The device asclaimed in claim 10, wherein said selection means comprise adiscriminator for separating the n1+β+1−α most significant bits of thesecond intermediate digital value, on the one hand, and the α leastsignificant bits of said second intermediate digital value, on the otherhand.
 12. The device as claimed in claim 10, wherein said selectionmeans comprise an operator for shifting to the right by α bits, whichreceives as input the n1+β+1 bits of the second intermediate digitalvalue, and which delivers as output the n1+β+1−α most significant bitsof the second intermediate digital value as a digital output value. 13.The device as claimed in claim 12, wherein said selection means furthercomprise means for applying to the second intermediate digital value amask having at most n1+β+1 bits, the n1+β+1−α most significant bits ofwhich are equal to the logical value 0 and the α least significant bitsof which are equal to the logical value 1, so as to select the α leastsignificant bits of said second intermediate digital value as thedigital error value.
 14. The device as claimed in claim 12, wherein saidselection means further comprise, on the one hand, an operator forshifting to the left by α bits, which receives as input the n1+β+1−αbits of the digital output value and delivers as output a thirdintermediate digital value encoded over at most n1+β+1 bits and, on theother hand, a difference operator which receives said third intermediatedigital value as a first operand and said first intermediate digitalvalue as a second operand, and which delivers as output the digitalerror value.
 15. The device as claimed in claim 8, wherein the errorsignal is delivered to the input of the adder means through a unitarydelay operator.
 16. A digitally modulated frequency synthesizer,comprising a phase-locked loop comprising a variable-ratio frequencydivider in a return path, wherein the division ratio is controlled by adigital value obtained in particular from a real value corresponding tothe central frequency of a radio channel, the synthesizer furthercomprising a conversion device as claimed in claim 8 for reducing thequantization error affecting said real value.